This invention relates to a semiconductor integrated circuit device and a method for making the same, and more particularly to, a method for making a CMOS integrated circuit device on a SOI (silicon on insulator) substrate and a master-slice type semiconductor integrated circuit device and a method for making the same.
In general, a conventional process of fabricating a CMOS semiconductor integrated circuit device that a CMOS circuit is formed on an ordinary silicon substrate requires eight patterns of patterning masks for forming (1) field oxide film, (2) n-well, (3) p-well, (4) gate electrode, (5) p-LDD layer, (6) n-LDD layer, (7) p-source, drain diffusion layers, and (8) n-source, drain diffusion layers, from the start of the process until the formation of transistor before the wiring process.
On the other hand, in a conventional SOI MOSFET fabrication process that a CMOS circuit is formed on a SOI substrate, the number of patterning masks can be reduced to a degree because well-forming steps are not necessary. However, the SOI substrate is more expensive than the silicon substrate. Therefore, for the purpose of reducing the manufacturing cost, it is desired that the number of steps in the SOI MOSFET fabrication process be further decreased.
Also, a CMOS master-slice type semiconductor integrated circuit device comprising an array of basic cells, each of which is composed of several MOSFETs, has been developed.
Thus, the first problem is that the conventional CMOS integrated circuit device using SOI substrate must have a high manufacturing cost. This is because SOI substrates are three to five times expensive comparing to ordinary silicon substrates. Therefore, the cost-down effect in fabricating the conventional CMOS integrated circuit device using SOI substrate, which is brought by that the well-forming process is omitted, is canceled by the high manufacturing cost of SOI substrate.
The second problem is that the integration density of elements must be reduced when the, conventional CMOS master-slice type circuit is formed on silicon substrate or SOI substrate. This is because the conductivity type of MOSFET channel cannot be changed in the customizing process. Namely, the conductivity type of active-region channel of MOSFET is determined at the time of well-forming in case of bulk CMOS and at the time of ion-implantation for adjusting Vt in case of SOI CMOS. Thus, the conductivity type of MOSFET channel is determined before the customizing process.
Accordingly, it is an object of the invention to provide a method for making a semiconductor integrated circuit device using SOI substrate that the number of steps is further decreased to reduce the manufacturing cost.
It is a further object of the invention to provide a master-slice type semiconductor integrated circuit device using SOI substrate that the integration density of elements is enhanced.
It is a still further object of the invention to provide a method for making a master-slice type semiconductor integrated circuit device using SOI substrate that the integration density of elements is enhanced and the number of steps is further decreased to reduce manufacturing cost.
According to the invention, provided is a method for making a semiconductor integrated circuit device used to form a p-channel MOS field-effect transistor and a n-channel MOS field-effect transistor on a common SOI substrate with a structure that a first silicon layer, insulating film and a second silicon layer are layered;
wherein the steps from sectioning a SOI layer as the second silicon layer by insulation separation into a plurality of active regions to forming at least one gate electrode to be laid through gate insulating film on the surface of each of the plurality of active regions are conducted with no relation to the conductivity type of MOS field-effect transistor.
According to another aspect of the invention, a master-slice type semiconductor integrated circuit device, comprises:
basic cells composed of a p-channel MOS field-effect transistor and/or a n-channel MOS field-effect transistor disposed in a plurality of adjacent active regions, the basic cells being formed on a SOI substrate that a first silicon layer, insulating film and a second silicon layer are layered;
wherein the arrangement of gate electrode on the active regions is common, and the master-slice type semiconductor integrated circuit device has different kinds of basic cells with different combinations of a p-channel MOS field-effect transistor and/or a n-channel MOS field-effect transistor.
According to another aspect of the invention, a method for making a master-slice type semiconductor integrated circuit device, comprises the steps of:
preparing a master substrate by conducting the steps from sectioning a SOI layer as a second silicon layer by insulation separation into a plurality of pairs of active regions to forming at least one gate electrode to be laid through gate insulating film on the surface of each of the plurality of active regions with no relation to the conductivity type of MOS field-effect transistor; and
customizing the master substrate according to a circuit desired by customers;
wherein the customizing step is conducted by disposing a p-channel MOS field-effect transistor and/or a n-channel MOS field-effect transistor in the pair of active region to form different kinds of basic cells with different combinations of a p-channel MOS field-effect transistor and/or a n-channel MOS field-effect transistor and conducting the wiring to a selected one of the basic cells.